As device nodes get smaller (for example, approaching dimensions of about 22 nm or less), manufacturing challenges become more apparent. For example, the combined thickness of barrier and seed layers of typical materials deposited in an opening prior to filling the opening, for example via electroplating, to form an interconnect structure may result in reduced efficiency of the electroplating process, reduced process throughput and/or yield, or the like.
Ruthenium, deposited for example by chemical vapor deposition (CVD), has become a promising candidate as a seed layer for a copper interconnect. However, ruthenium by itself cannot be a copper barrier and barrier layers such as TaN/Ta are still needed prior to ruthenium deposition. Alternatively, copper-manganese, deposited for example by physical vapor deposition (PVD), self-aligned barrier schemes have also gained in popularity as a desirable approach to the barrier solution. However, the inventors have observed that these two schemes each have manufacturability difficulties.
For CVD ruthenium, the deposition rate is very slow without O2 as reducing gas. However, the O2 gas tends to oxidize the tantalum-based barrier layer, resulting in increase via resistance. Therefore, with TaN/Ta as barrier, throughput with CVD ruthenium will be very slow. In addition, deposition of ruthenium without O2 also results in high carbon contaminated ruthenium films, which also increases line/via resistance. A high resistivity ruthenium film is not adequate for a seed layer, which is the main merit of the ruthenium seed layer.
With respect to the Cu—Mn process (a physical vapor deposition, or PVD, process), copper can diffuse into the oxide layer, especially low-k oxide, during the deposition steps, causing reliability issues.
Thus, the inventors have provided improved methods for forming barrier/seed layers for interconnect structures.